Most previous logic systems, such as Boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. In traditional Boolean logic that uses a CMOS or TTL implementation, a low voltage level on a signal line means "logic false" or the number "zero." A high voltage level on the same line means "logic true" or the number "one." Thus a signal line may assume one of two values, either of which ostensibly has meaning.
Typically, a sequential logic circuit will respond to a grouped set of inputs to generate an output. While a set of input signals propagates through the sequential circuit, the sequential circuit output is unreliable for a period of time corresponding to worst-case propagation delays through the individual logic gates. In traditional clocked Boolean logic circuits, however, a binary signal might--or might not--be valid at any given moment. Outputs of combinational circuits have a period of uncertainty during which input signals propagate through gates. Designers accommodate such periods of instability by analyzing the worst-case propagation delays through such circuits and sampling the signal only at predetermined times when the output is expected to be stable, often by latching the output into a register. The sampling time is determined by an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
While these traditional synchronous circuits have become the dominant class of logic, a substantial amount of design analysis is necessary to avoid a variety of timing-related problems, such as worst-case propagation delay and race conditions. In addition, the proportion of power and wafer area ("real estate") that must be devoted to clocking has become substantial, and in certain instances can be a limiting factor to the total amount of functionality that can be integrated onto a single chip.